In computer architecture applications, processors often use caches and other memory local to the processor to access data during execution. The processors more efficiently execute instructions when, for example, program data (e.g., machine code) and data (e.g., operands) accessed by a processor are stored locally in a cache. However, a local cache often accesses a shared memory which can result in contention issues that arise when multiple requesters try to access a shared memory resource. The problem is compounded when multiple caches (often having differing line sizes and timing requirements) of multiple processors are used together in a multiprocessor system. Speculative fetches from various memory controllers in a multiple processor system also contend for the same downstream memory resources.
The problems noted above are solved in large part by a prefetching system that allows downstream memory controllers to arbitrarily cancel various speculative prefetches. The disclosed prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource in certain conditions.